1. Field of the Invention
The present invention relates to thin films suitable as dielectrics in IC's and for other similar applications. In particular, the invention concerns thin films comprising compositions obtainable by hydrolysis of two or more silicon compounds, which yield an at least partially cross-linked siloxane structure. The invention also concerns a method for producing such films by preparing siloxane compositions by hydrolysis of suitable reactants, by applying the hydrolyzed compositions on a substrate in the form of a thin layer and by curing the layer to form a film.
2. Description of Related Art
Built on a semiconducting substrate, integrated circuits comprise of millions of transistors and other devices, which communicate electrically with one another and outside packaging material through multiple levels of vertical and horizontal wiring embedded in a dielectric material. Within the multilayer metallization structure, “vias” comprise the vertical wiring, whereas “interconnects” comprise the horizontal wiring. Fabricating the metallization can involve the successive depositing and patterning of multiple layers of dielectric and metal to achieve electrical connection among transistors and to outside packaging material. The patterning for a given layer is often performed by a multi-step process consisting of layer deposition, photoresist spin, photoresist exposure, photoresist develop, layer etch, and photoresist removal on a substrate. Alternatively, the metal may sometimes be patterned by first etching patterns into a dielectric, filling the pattern with metal, then subsequently chemical mechanical polishing the metal so that the metal remains embedded only in the openings of the dielectric. As an interconnect material, aluminum has been utilized for many years due to its high conductivity (and low cost). Aluminum alloys have also been developed over the years to improve the melting point, diffusion, electromigration and other qualities as compared to pure aluminum. Spanning successive layers of aluminum, tungsten has traditionally served as the conductive via material. Silicon dioxide (dielectric constant of around 4.0) has been the dielectric of choice, used ill conjunction with aluminum-based and tungsten-based interconnects and via for many years.
The drive to faster microprocessors and more powerful electronic devices in recent years has resulted in very high circuit densities and faster operating speeds, which in turn have required higher conductivity metals and lower-k dielectrics (preferably below 3.0, more preferably below 2.5 dielectric constant). In the past few years, VLSI (and ULSI) processes have been moving to copper damascene processes where copper (or copper alloys) is used for the higher conductance in the conductor lines and spin-on or CVD low-k dielectrics are used for the insulating material surrounding the conductor lines. To circumvent problems with etching, copper along with a barrier metal is blanket deposited over recessed dielectric structures consisting of interconnect and via openings and subsequently polished in a processing method known as “dual damascene.” The bottom of the via opening is usually the top of an interconnect from the previous metal layer or in some instances, the contacting layer to the substrate.
In addition to the dielectric IC material being photopatternable, it is also desirable that the material be easy to deposit or form, preferably at a high deposition rate and at a relatively low temperature. Once deposited or formed, it is desirable that the material be easily patterned, and preferably patterned with small feature sizes if needed. Once patterned, the material should preferably have low surface and/or sidewall roughness. It might also desirable that such materials be hydrophobic to limit uptake of moisture (or other fluids), and be stable with a relatively high glass transition temperature (not degrade or otherwise physically and/or chemically change upon further processing or when in use).
Summarizing: aside from possessing a low dielectric constant, the ideal dielectric should afford the following properties:    1) A high modulus and hardness in order to bind the maze of metal interconnects and vias together as well as abet chemical mechanical polishing processing steps.    2) Low thermal expansion, typically less than or equal to that of Al interconnects.    3) Excellent thermal stability, generally in excess of 425° C.    4) No cracking, excellent fill and planarization properties    5) Excellent adhesion to dielectric, semiconductor, and metal materials.    6) Sufficient thermal conductivity to dissipate joule heating from interconnects and vias.    7) Material density that precludes absorption of solvents, moisture, or reactive gasses.    8) Allows well-defined vertical etch profiles at very small dimensions.    9) Low current leakage, high breakdown voltages, and low loss-tangents.    10) Stable interfaces between the dielectric and contacting materials.
By necessity, low-k materials are usually engineered on the basis of compromises. Silicate-based low-k materials can demonstrate exceptional thermal stability and usable modulus but can be plagued by brittleness and cracking. In contrast, organic materials often show improved material toughness, but at the expense of increased softness, lower thermal stability, and higher thermal expansion coefficients. Porous materials sacrifice mechanical properties and possess a strong propensity for absorbing chemicals used in semiconductor fabrication leading to reliability failures. Fluorinated materials can induce corrosion of metal interconnects, rendering a chip inoperative. Universally, low-k materials sacrifice mechanical robustness and thermal conductivity with respect to their pure silicon dioxide analogues, making integration into the fabrication flow very challenging.
Further, known materials comprising exclusively inorganic bonds making up the siloxane matrix are brittle and have poor elasticity at high temperatures.